Semiconductor Integrated Circuits Layout Design Act : Penalty for falsification of entries in the

Semiconductor Integrated Circuits Layout Design Act,2000

Act No : 37

Section : Penalty for falsification of entries in the register.

59. Penalty for falsification of entries in the register.-If any person makes, or causes to be made, a false entry in the register, or a writing falsely purporting to be a copy of an entry in the register, or produces or tenders, or causes to be produced or tendered, in evidence any such writing, knowing the entry or writing to be false, he shall be punishable with imprisonment for a term which may extend to two years, or with fine, or with both.